1. Field of the Invention
The present invention relates to power distribution schemes in integrated circuit chips (ICs), and specifically, to a novel power distribution network for ICs that exhibits increased electromigration resistance while maintaining redundancy and lower resistance.
2. Discussion of the Prior Art
Power for integrated circuits is usually distributed on a chip by a grid of continuous metal lines. Typically, there are two separate grids; one at ground potential and one at Vdd.
As illustrated in FIG. 1(a), a "continuous" grid 12 may be formed from orthogonal sets of lines on respective two different wiring levels in the chip. Specifically, a set of parallel lines 8a, 8b for example, is patterned at one chip wiring level and are connected to a second orthogonal set of lines 10a, 10b on the second wiring level via studs so as to form the continuous grid. In present chip designs, the length of the lines is determined by the size of the area over which power must be distributed which may be many hundreds of microns. The power grids must satisfy several different requirements: First, the resistance of the grid must be kept low to avoid unwanted voltage drops during chip operation. The grid must also have sufficient redundancy to permit easy connection of devices in regions of the chip where the inclusion of additional components disrupts the continuous grid. Finally, the electromigration resistance of the lines in the grid must be sufficient to ensure the reliability of the interconnects at intended current densities. In some instance, the electromigration resistance of the lines becomes the limiting factor and determines the dimensions of the lines that must be used for the grid.
Other prior art power distribution schemes, such as shown in FIG. 1(b) and described in detail in U.S. Pat. No. 5,742,099 to Debnath et al., comprise short length lines 11a, 11b interconnected via studs to other layers. However, the shorter line segments are employed and implemented for the purpose of enhancing wireability of an integrated circuit, i.e., decreasing area of the integrated circuit. Particularly, maximizing wireability requires the introduction of gaps in the normally continuous conductors that lie upon a line perpendicular to the short segments. U.S. Pat. No. 5,742,099 thus teaches the segmentation of the power and ground busses to improve wireability of control logic using automatic routing tools, however does not recognize, teach or suggest the benefits of increased electromigration resistance and greater grid redundancy.
It has been observed by Filippi et al. in "The Effect of Current Density and Stripe Length on Resistance Saturation during Electromigration Testing", Applied Physics Letters Vol. 69 (16), p. 2350, Oct. 14, 1996, that short segments may limit the amount of electromigration damage that may occur in a conducting line at a given current density, thus, permitting larger currents to be used in designs using only short line segments.
It would be highly desirable to provide a power grid and distribution network structure for integrated circuit (IC) devices that exhibits increased electromigration resistance while still maintaining the redundancy and low resistance of the grid.
Moreover, it would be highly desirable to provide a grid structure that exhibits increased electromigration resistance by including diffusion blocking interlevel contacts and employing a regular array with "phase shift" between adjacent tracks of segmented power busses.